A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store a data bit. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline.
In a semiconductor memory device of the type described above, data may be written to or read from the memory cells of the array using a memory cycle that is divided into an active phase and a precharge phase, with the active phase being used to read or write one or more memory cells of the array and the precharge phase being used to precharge the bitlines to a precharge voltage in preparation for the next cycle. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline.
For a given read or write operation, the corresponding memory cycle is more particularly referred to as a read cycle or a write cycle, respectively. In certain types of memory devices, such as static random access memories (SRAMs), the read and write cycle times are not equal. The read access time is typically longer than the write access time, while the write precharge time is longer than the read precharge time.
As is well known to those skilled in the art, read and write self-time tracking arrangements may be used in order to establish appropriate signal timing for respective read and write operations. Such self-time tracking functionality is often designed to control the read and write signal timing over expected process, voltage and temperature (PVT) variations. This is particularly important for high-speed operations having read and write cycle frequencies in the gigahertz (GHz) range.
A conventional self-time tracking arrangement of this type utilizes a dummy row of memory cells and a dummy column of memory cells, associated with a dummy wordline and a dummy bitline, respectively, with those memory cells being configured in substantially the same manner as the actual memory cells of the memory array. A dummy wordline driver generates a dummy wordline signal for application to the dummy wordline with substantially the same timing as an actual wordline signal applied to an actual wordline of the memory array. The dummy wordline and dummy bitline are also known as a self-time wordline (STWL) and a self-time bitline (STBL), respectively.
The signal delay of the dummy wordline due to its resistor-capacitor (RC) time constant is designed to match the corresponding RC signal delay of the actual wordline of the memory array. Also, the wordline loading impact of the dummy column is designed to match the wordline loading impact of an actual bitline of the memory array.
In order to permit independent control of the read and write cycle times, self-time tracking circuitry may be separated into two paths, one for read and another for write. This approach is also called dual mode self-time (DMST).
Conventional self-time tracking arrangements of the type described above can suffer from a number of drawbacks. For example, in one such arrangement, the write cycle time of the actual memory cells is tracked by writing a data bit at one binary logic level to a dummy memory cell in the first half of a given write cycle and then writing a data bit of the opposite logic level to the dummy memory cell in the second half of the write cycle. This generally leads to a write cycle time that is approximately twice the write access time. However, since the write cycle time is the combination of the write access time and the precharge time, and the precharge time is typically less than the write access time, the write cycle time in this arrangement is higher than it should be, which unduly limits the performance of the memory device. Also, this arrangement can fail to accurately track wordline and bitline load, and actual memory cell configuration during write.